The lower effective mass and higher mobility of carriers in germanium (Ge) as compared to silicon (Si) has prompted renewed interest in Ge-based devices for high performance logic, especially as it becomes increasingly difficult to enhance Si complementary metal oxide semiconductor (CMOS) performance through traditional scaling. Typically, Ge has a 2× higher mobility for electrons and a 4× higher mobility for holes than a conventional Si material. One major roadblock for Ge CMOS device fabrication is that it is very difficult to obtain a stable gate dielectric. A water-soluble native Ge oxide that is typically present on the upper surface of a Ge-containing material causes the instability of the gate dielectric.
The recent developments of high-quality deposition techniques, such as atomic layer deposition (ALD) and metal-organic chemical vapor deposition (MOCVD), to deposit dielectric films with high dielectric constants (on the order of about 4.0 or greater, typically about 7.0 or greater) for the replacement of SiO2 in Si metal oxide semiconductor field effect transistors (MOSFETs) has prompted activities to develop Ge MOSFETs implementing such dielectrics. The final surface preparation before high k film deposition is critical to the final MOS device performance.
For Ge, specifically, it appears essential to have a surface free (i.e., devoid) of germanium oxide before high k film deposition. A conventional solution for Si has been to use (concentrated or dilute) hydrofluoric acid (e.g., HF or DHF) to remove any native Si oxide, while leaving an H-passivated surface. Despite being successful for Si CMOS device fabrication, this surface passivation technique was found to be less effective on Ge. See, for example, D. Bodlaki, et al. “Ambient stability of chemically passivated germanium interfaces”, Surface Science 543, (2003) 63-74. For high dielectric constant films such as, for example, HfO2 and Al2O3, deposited onto HF or DHF treated materials, poor electronic properties of the gate stack are typically found. Other acid treatments, such as HCl, result in similarly poor electrical characteristics. This is illustrated by a set of C-V characteristics (see, FIG. 1) of an exemplary gate stack that was fabricated by (i) providing an epi-ready Ge (100) material; (ii) wet chemical cleaning by ozonated deionized (DI) water for 60 seconds, followed by addition of HCl to the solution for 60 seconds, and then DI water rinse for 300 seconds; (iii) deposition of 50 Å HfO2 by ALD from Al(CH3)3 and water vapor at 300° C.; and (iv) evaporation of Al dots using a shadow mask to form MOS capacitors.
The high frequency dispersion and low capacitance modulation between accumulation and inversion are a strong indication of a very high areal density of interface states (Dit). This low electronic quality of the interface probably arises from the formation of undesirable interfacial compounds. Usually, germanium oxide (GeO2) is held responsible, but Hf germanate or other compounds are possible candidates.
One demonstrated method to fabricate functional gate stacks is to desorb the Ge oxide in an ultra-high vacuum (UHV) system at high temperatures (e.g., at 400° to 650° C.) followed by in-situ high k deposition. X.-J. Zhang, et al., J. Vac. Sci. Technology A11, 2553 (1993) describe thermal desorption of Ge oxide, while J. J.-H. Chen, et al. IEEE Trans. Electron Dev. 51, 1441, (2004) describe the in-situ deposition process. The main drawback of this approach is that UHV systems are costly and generally incompatible with standard ALD or MOCVD high k deposition tools used in manufacturing. A practical solution is based on nitridation of a wet-etched (e.g., using DHF) Ge surface prior to dielectric deposition using either atomic N exposure or a high-temperature NH3 gas treatment. See, for example, Chi On Chui, et al., IEEE Electr. Device Lett. 25, 274 (2004), E. P. Gusev, et al., Appl. Phys. Lett. 85, 2334 (2004) and N. Wu, et al. Appl. Phys. Lett. 84, 3741 (2004).
That nitrided stacks can be functional is exemplified by the C-V characteristics (see FIG. 2) of a gate stack fabricated in the same way as the stack discussed above in connection with FIG. 1, however, with an additional NH3 treatment (at 650° C. for 1 minute) added between the wet HCl clean and HfO2 deposition. The characteristics shown in FIG. 2 indicate greatly improved electrical characteristics than those shown in FIG. 1. Moreover, the characteristics illustrated in FIG. 2 show only a small frequency dispersion as compared to FIG. 1 indicating that the interface density had been reduced. The hysteresis is due to some dielectric traps in the HfO2 film. However, despite the success in reducing the interface state density, the nitridation induces fixed positive charge at the interface which causes a large negative flatband shift and could degrade the device mobility. The nitridation step also has the disadvantage of requiring high-temperatures which could lead to unwanted dopant diffusion and interface reactions.
Sulfur passivation of Ge surfaces using an aqueous ammonium sulfide (NH4)2S treatment (with other solvents such as methanol optionally added) has been described in the literature. See, for example, G. W. Anderson, et al., Appl. Phys. Lett. 66, 1123 (1995); P. F. Lyman, et al., Surf. Sci. 462, L594 (2000); D. Bodlaki, et al., J. Chem. Phys. 119, 3958 (2003); and Bodlaki, et al. Surf. Sci. 543, 63 (2003). The sulfur or germanium sulfide (GeSix) layer thus created using these techniques has a thickness of up to 3 monolayers. However, no application to MOSFET or MOS device fabrication of high k dielectric deposition has been suggested or demonstrated. Furthermore, the aforementioned cited literature does not indicate whether S treatment could be used for high k gate stack passivation.
In view of the above, it would be highly advantageous to have a method of preparing a Ge/high k interface that offers the following attributes:                1. low temperature passivation, so that the Ge FET fabrication flow could be milder, reducing unwanted diffusion or reaction;        2. wet-chemical application to provide process simplicity and reduce cost; and        3. improved electrical characteristics including a low interface state density and low flatband shift.        